(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a vertical type bipolar transistor structure and a method for fabricating the same.
(2) Description of the Related Art
For high-speed bipolar transistors, it is important to enhance cut-off frequency and to decrease parasitic capacitance and parasitic resistance. One way to accomplish this is to employ a vertical type bipolar transistor structure with a self-aligned film forming technique used to the fullest extent in the fabrication thereof. The inventor together with other authors, that is, F. Sato et al., proposed one of such bipolar transistor structures under the title "A self-aligned selective MBE technology for high-performance bipolar transistors" in IEDM Technical Digest, pp. 607-610 (1990). The proposal relates to a self-aligned bipolar transistor with an epitaxial Si base layer using "self-aligned" selective MBE technology, which the authors call SSSB (Super Self-aligned Selectively grown Base) technology.
The proposed bipolar transistor referred to above is configured as shown in FIG. 1 which is a diagrammatic sectional view thereof.
On the surface of a p.sup.- -type silicon substrate 201, a buried n.sup.+ -type layer 202 is selectively provided. The entire surface of a p.sup.- -type silicon substrate 201 is covered by an n.sup.- -type silicon epitaxial layer 203. This n.sup.- -type silicon epitaxial layer 203 is isolated by a LOCOS type silicon oxide film 204. A surface of the n.sup.- -type silicon epitaxial layer 203 is entirely covered by an insulating film 206. There is a phosphorus diffusion layer (not shown) which reaches the n.sup.+ -type buried layer 202 through an opening (not shown) provided in the insulating film 206. This phosphorus diffusion layer constitutes a collector plug region and has a phosphorus concentration not less than 10.sup.19 cm.sup.-3. On the insulating film 206, there are selectively provided a base leading electrode 207 of a p.sup.+ -type polycrystalline silicon film and a collector leading electrode (not shown) of an n.sup.+ -type polycrystalline silicon film. This collector leading electrode is connected to the phosphorus diffusion layer through the opening. The surfaces of the insulating film 206, the base leading electrode 207 and the collector leading electrode are covered by an insulating film 209.
A first window 262 is provided extending through the insulating film 209 and the base leading electrode 207, and a spacer 213 in an insulating material is provided at sides of the window 262. A second window 263 larger than the first window 262 in a predetermined width (in sectional view) is provided in the insulating film 206. The second window 263 provides an overhang portion of the base leading electrode 207. An intrinsic base layer 221 formed of a p-type monocrystalline semiconductor layer and self-aligned with the second window 263 covers the n.sup.- -type silicon epitaxial layer 203. A p-type polycrystalline semiconductor connecting layer 231 is provided in such a way that an upper face thereof is self-aligned to an under surface of the base leading electrode 207, the under surface being an exposed surface of the overhang portion, and an under face thereof is in contact with the intrinsic base layer 221. The p-type monocrystalline semiconductor layer constituting the intrinsic base layer 221 is selectively grown on a surface of the n.sup.- -type silicon epitaxial layer 203 using, for example, an MBE growth method. The intrinsic base layer 221 is constituted by, for example, a p-type monocrystalline semiconductor silicon layer. In the MBE growth, the polycrystalline semiconductor layer selectively grows-on the under face of the base leading electrode 207, the under face being an exposed surface of the overhang portion of the base leading electrode 207.
A spacer 214 formed of an insulating film covers an exposed surface of the above-mentioned spacer 213. An emitter layer 241 formed of an n-type monocrystalline semiconductor layer is self-aligned with the spacer 214 on a surface of the intrinsic base layer 221. In the window 262 and other windows or openings (not shown) which extend to the base leading electrode 207 and the collector leading electrode provided in the insulating film 209, there are provided such elements as aluminum alloy electrodes 215 which are respectively connected to layers such as the emitter layer 241.
In the conventional bipolar transistor described above, the emitter layer 241 formed results in a size of (opening width of the window 262)-2.times.[(film thickness of the spacer 213)+(film thickness of the spacer 214)]. The opening width of the window 262 is larger than the sum of thicknesses of the spacers 213 and 214 and the precision of the dimension of the opening width thus formed is dependent on the precision of photolithography (the precision in photoresist patterns and that in dry etching). That is, the dimension precision of the thus finished emitter layer 241 formed is greatly dependent on the finished opening width of the window 262.
In the conventional bipolar transistor having the above configuration, the emitter layer whose finished dimension is minute or fine suffers from a low dimension precision. For example, when the lithography precision (absolute error) is .+-.0.05 .mu.m and the emitter layer is to be formed to a dimension smaller than about 0.5 .mu.m, the relative error in the dimension of the emitter layer will be larger than about 10%. Therefore, in the emitter layer having a minute finished dimension, there will be a large variations in current values (proportional to an area of the emitter layer) of the transistor.